Parution "Logical Time @ Work for the (...)

Rubrique : Nice Universitaire

Frédéric Mallet

Maître de Conférences, département Informatique, UNS

Éditeur : LAP LAMBERT Academic Publishing

ISBN-13 : 978-3-8433-9388-1

Langue : anglais

Résumé :

Logical time is a relaxed form of time promoted by synchronous languages that is functional, elastic (can be abstracted or refined), and multiform. All these properties make logical time adequate also at design time, whereas precise physical time annotations should only matter in later post-synthesis stages. The Clock Constraint Specification Language (CCSL) is a concrete language dedicated to the modeling and analysis of logical time properties. CCSL was initially defined as a companion for the time model of the UML profile for MARTE. It has now become a full-fledged domain-specific modeling language for capturing causal, chronological and timed relationships. It should complement other syntactic models to capture their underlying model of computation. This book starts by describing the historical models of concurrency that have inspired the construction of CCSL. Then, CCSL is introduced and used to build libraries dedicated to two emerging standard models from the automotive (East-ADL) and the avionic (AADL) domains. Finally, an observer-based technique to verify Esterel and VHDL implementations against CCSL specifications is presented.

À propos de l’auteur :

Frédéric Mallet est Maître de Conférences au département Informatique de l’Université Nice Sophia Antipolis. Il est membre du projet Aoste, commun entre le laboratoire I3S (UMR CNRS) et le centre de recherche INRIA Sophia Antipolis. Il s’intéresse à la définition de modèles formels pour la conception et l’analyse de systèmes temps réel et embarqués.


L’adresse originale de cet article est